Multiple functions are today commonly being integrated onto a single system chip. When initially defining architecture for integration of multiple discrete components onto a single chip, access to external devices can be a critical issue. For example, an MPEG video decoder system often employs external memory for various data areas, or buffers such as frame buffers. This external memory is typically implemented using either DRAM or SDRAM technology. In the decoder system, a video decode unit requires immediate access to external memory when needed to prevent starving the video display or on-screen graphics. If the video decoder's request for data is delayed, the picture could be corrupted. Likewise, an on-chip processor, if held from accessing external memory when needed could experience significant performance degradation.
Two approaches are typical in the art for accessing off-chip devices. In a first approach, each on-chip functional unit is given access to the needed external device(s) through a data bus dedicated to that particular unit. Although locally efficient for accessing the external device, globally within the integrated system this approach can be less than optimal. For example, although each function will have complete access to its own external memory area, there is no shared access between functions of the integrated system. Thus, transferring data from one memory area to another memory area of the system is often needed. This obviously increases data transfers and can thus degrade performance of the overall system, i.e., compared with a shared memory system.
Another approach is to employ a single common bus within the integrated system which allows one or more functional units of the system to communicate to external memory through a single port. Although allowing the sharing of memory, the difficulty with this approach arises when many functions are integrated onto a single chip, with each function requiring a certain amount of bandwidth for accessing off-chip data. In implementation, the bandwidth of the single data bus needs to be sufficient to accommodate all functional units communicating through the bus. This bandwidth requirement can become prohibitive. For example, in a video decode system, a video decode unit may require 100 Mbytes/sec of bandwidth, while a transport unit may require up to 5 Mbytes/sec of bandwidth, a processor unit up to 50 Mbytes/sec and an audio decoder up to 5 Mbytes/sec. Thus, with a single data bus serving these functional units, 160 Mbytes/sec of bandwidth would be needed. Further, in this example, each functional unit may be required to possess a large amount of internal buffering to span the time gap between memory accesses resulting from having multiple functions sharing communications through the single bus. These bandwidth and buffer requirements associated with the single bus implementation make the single bus/port implementation less than ideal for today's ever more integrated technologies.
Therefore, there exists a need in the art for an enhanced shared access control approach for an integrated system which allows multiple functions of the integrated system to simultaneously access different external devices through multiple ports while avoiding the performance degradation and increased costs inherent in a separate, dedicated port approach to accessing the external devices.